# Maintainer: Felix Yan <felixonmars@archlinux.org>
# Contributor: Marcin (CTRL) Wieczorek <marcin@marcin.co>
# Contributor: Jeffrey Tolar <tolar.jeffrey at gmail dot com>

pkgname=verilator
pkgver=4.212
pkgrel=1
pkgdesc='The fastest free Verilog HDL simulator'
url='https://www.veripool.org/projects/verilator/wiki/Intro'
arch=('x86_64')
license=('LGPL')
depends=('perl')
optdepends=('systemc')
makedepends=('python' 'systemc')
source=("https://github.com/verilator/verilator/archive/v$pkgver/$pkgname-$pkgver.tar.gz")
sha512sums=('efa6d38a1a2e4bde67fd2914f3fb88ea2f7d7d40b9309932ce1e307dfeccd3fefb4fbf3fd5e277232e0fc1ed315b5aa65ae48e6f567c14db0b84e245e9c02095')

prepare() {
  cd verilator-$pkgver
  sed -i 's/#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17)/_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17)/' configure.ac
  autoconf
}

build() {
  cd verilator-$pkgver
  ./configure --prefix=/usr
  make
}

check() {
  cd verilator-$pkgver
  make test
}

package() {
  cd verilator-$pkgver
  make install DESTDIR="$pkgdir"
}
